Generally in the electronic computers which use a large scale integrated circuit device (described as LSI hereinafter), the circuits in the LSI and those outside the LSI (described as internal circuits and external circuits hereinafter, respectively) are driven by power supply voltages having different voltage levels. The LSI as described above has an input/output circuit having a function for converting a signal level. Namely, the input/output circuit having the signal level converting function has a function for converting a voltage level of a signal supplied from a device operating with a power supply voltage inside the LSI and outputting the signal to an external circuit operating with a power supply voltage different from that within the internal circuit, and a function for converting a voltage level of a signal supplied from a device operating with an external different power supply voltage to a signal level for the internal circuit and delivering the signal to the internal circuit.
FIG. 7 is a circuit diagram showing configuration of an input/output circuit based on the conventional technology as described above. This input/output circuit comprises an output buffer circuit 12g (a circuit section enclosed with a bold dashed line) having an input circuit section 10g (a circuit section enclosed with a dotted line) and an output circuit section 11g (a circuit section enclosed with a dot and dash line), and an input buffer circuit 8, and is connected to an input/output terminal (PAD) 4 used for signal transactions with an external circuit not shown herein and a static electricity protection circuit 7.
The input circuit section 10g comprises an input terminal 1 for receiving an output signal IN1 outputted from an internal circuit to an external circuit from the internal circuit; a first control terminal 2 for receiving a first control signal IN2 from the internal circuit; a second control terminal 3 for receiving a second control signal IN3 from the internal circuit; four inverters G71, G73, G76 and G77; two double-input NOR gates G72 and G75; a double-input NAND gate G74; four P-channel metal oxide semiconductor transistors (described as PMOS transistor hereinafter) MP1, MP2, MP3 and MP4; and four N-channel metal oxide semiconductor transistors (described as NMOS transistor hereinafter) MN1, MN2, MN3 and MN4. On the other hand, the output circuit section 11g comprises two inverters G78 and G79, a PMOS transistor MP11, and a NMOS transistor MN11.
In FIG. 7, the side of the internal circuit (left side in the figure) from the phantom line positioned substantially at the center is a circuit (described as VDD1 circuit hereinafter) driven by a first power supply potential VDD1 as a power supply voltage for the internal circuit, while the side of the external circuit (right side in the figure) from the phantom line is a circuit (described as VDD2 circuit hereinafter) driven by a second power supply potential VDD2 (&gt;first power supply potential VDD1&gt;ground potential GND).
Namely, the VDD1 circuit includes the input terminal 1; first control terminal 2; second control terminal 3; four inverters G71, G73, G76 and G77; two NOR gates G72 and G75; and NAND gate G74 in the input circuit section 10g, while the VDD2 circuit includes the four PMOS transistors MP1, MP2, MP3 and MP4; four NMOS transistors MN1, MN2, MN3 and MN4 in the input circuit section 10g; and the output circuit section 11g.
In FIG. 7, designated at 5 is a second power supply terminal for supplying the second power supply potential VDD2, at 6 a ground terminal for the ground potential GND; and at N71, N72, N73, N74, N75, N76, N77 and N78 are nodes.
The first control signal IN2 inputted from the internal circuit through the first control terminal 2 is inputted into a first input terminal of the NOR gate G72 through the inverter G71. While the second control signal IN3 inputted from the internal circuit through the second control terminal 3 is inputted into a second input terminal of the NOR gate G72. An output signal from this NOR gate G72 is inputted into a first input terminal of the NAND gate G74.
Inputted into a second input terminal of this NAND gate G74 is the output signal IN1 inputted from the internal circuit through the input terminal 1. Further, output signal from the NAND gate G74 is inputted into the gate of the first NMOS transistor MN1 through the inverter G76 and also into the gate of the second NMOS transistor MN2.
The first NMOS transistor MN1 and the first PMOS transistor MP1 constitute a CMOS structure, and their drains are connected to each other. The sources of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected to the second power supply 5 and the ground 6, respectively. The second NMOS transistor MN2 and the second PMOS transistor MP2 constitutes a CMOS structure, their drains are connected to each other, and the sources of the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected to the second power supply terminal 5 and the ground terminal 6, respectively.
The drain of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2. While the drain of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1 and also connected to the output circuit section 11g through the node N75. A pair of CMOSs comprising those first and second PMOSs and NMOSs each constitutes a latch-type of signal level converting circuit for performing level conversion of a signal for the level of the first power supply potential VDD1 outputted from the LSI-internal circuit to a signal for the level of the second power supply potential VDD2.
On the other hand, an output signal from the NOR gate G72 is inputted into the first input terminal of the NOR gate G75 through the inverter G73, and the output signal IN1 having been inputted through the input terminal 1 is inputted into the second input terminal of the NOR gate G75. An output signal from this NOR gate G75 is inputted into the gate of the third NMOS transistor MN3 through the inverter G77 and also inputted into the gate of the fourth NMOS transistor MN4.
The third NMOS transistor MN3 and the third PMOS transistor MP3 constitute a CMOS structure, and their drains are connected to each other. The sources of the third PMOS transistor MP3 and the third NMOS transistor MN3 are connected to the second power supply terminal 5 and the ground terminal 6, respectively. The fourth NMOS transistor MN4 and the fourth PMOS transistor MP4 also constitutes a CMOS structure, their drains are connected to each other, and the source of the fourth PMOS transistor MP4 and the source of the fourth NMOS transistor MN4 are connected to the second power supply terminal 5 and the ground terminal 6, respectively.
The drain of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4. While the drain of the fourth PMOS transistor MP4 is connected to the gate of the third PMOS transistor MP4 and also connected to the output circuit section 11g through the node N76. A pair of CMOSs each comprising those third and fourth PMOS and NMOS constitutes a latch-type of signal level converting circuit for performing level conversion of a signal for the level of the first power supply potential VDD1 outputted from the LSI-internal circuit to a signal for the level of the second power supply potential VDD2.
Each output from the drains of the second PMOS transistor MP2 and the fourth PMOS transistor MP4 is inputted into the gate of the PMOS transistor MP11 and the gate of the NMOS transistor MN11 respectively, both of which constitute a CMOS structure, through the inverter G78 and inverter G79, respectively, in the output circuit section 11g. Those sources of the PMOS transistor MP11 and the NMOS transistor MN11 are connected to the second power supply terminal 5 and the ground terminal 6, respectively. The drains of the PMOS transistor MP11 and the NMOS transistor MN11 are connected to each other and are further connected to the input/output terminal 4, the static electricity protection circuit 7, and the input buffer circuit 8.
Herein, each gate insulating film of the MOS transistors, constituting the five PMOS transistors MP1, MP2, MP3, MP4 and MP11, five NMOS transistors MN1, MN2, MN3, MN4 and MN11, and two inverters G78 and G79 in the output circuit section 11g, respectively, is formed so that each of the films is thicker than gate insulating film of MOS transistors each constituting the four inverters G71, G72, G76 and G77, two NOR gates G72 and G75, and NAND gate G74, respectively, by which occurrence of dielectric breakdown is prevented.
The input buffer circuit 8 is connected to an unillustrated internal circuit and comprises a circuit for converting a signal level from an external input signal indicating definition of HIGH as a relatively high potential level and LOW as a relatively low potential level by the second power supply potential VDD2 and the ground potential GND to a signal indicating definition of HIGH and LOW by the first power supply potential VDD1 and the ground potential GND; and an input driver circuit.
The static electricity protection circuit 7 operates so as to protect the input/output circuit from the static electricity, enters in a low impedance state when a high potential external input signal is received from the input/output terminal 4, and enters in a high impedance state when a low potential external input signal or an operation voltage is received therefrom. The static electricity protection circuit 7 is formed, for example, by combining resistors each using a junction diode, diffusion area, and a polysilicon layer on a semiconductor substrate.
Description is made for effects of the input/output circuit configured as shown in FIG. 7. This input/output circuit delivers a signal from the internal circuit in the LSI to a device outside the LSI while it is converting a signal level. Namely, the internal circuit in the LSI operates by a first power supply unit system with the first power supply potential VDD1 and the ground potential GND supplied thereto, and supplies a signal supplied from the internal circuit thereof, of which the level is converted, to a device outside the LSI operated by a second power supply unit system with the second power supply potential VDD2 and the ground potential GND supplied thereto. This operation will be described separately in an input mode and an output mode.
[Input Mode]
When the first control signal IN2 is LOW (L), the signal for HIGH (H) obtained through inversion thereof by the inverter G71 is inputted into the NOR gate G72. The output from the NOR gate G72 (namely, potential at the node N71 and input into the NAND gate G74) is always LOW regardless of the level of the second control signal IN3. The output from the NAND gate G74 (namely, potential at the node N73) is always HIGH regardless of the level of the output signal IN1, and this level is inverted to be LOW by the inverter G76.
Accordingly, the first NMOS transistor MN1 becomes OFF, the second NMOS transistor MN2 becomes ON, the first PMOS transistor MP1 becomes ON and the second PMOS transistor MP2 becomes OFF, and the input into the inverter G78 (the potential of the node N75) is LOW. This LOW level is inverted by the inverter G78, and as the output (namely, potential at the node N77) therefrom becomes HIGH the PMOS transistor MP11 in the output circuit section 11g becomes OFF.
On the other hand, as the potential level of the node N71 is inverted by the inverter G73, the input into the NOR gate G75 (namely, potential at the node N72) is HIGH. The output from the NOR gate G75 (namely, potential at the node N74) is always LOW regardless of the level of the output signal IN1, and this level is inverted to HIGH by the inverter G77.
Accordingly, the third NMOS transistor MN3 becomes OFF and the fourth NMOS transistor MN4 becomes ON, further the fourth PMOS transistor MP4 becomes OFF and the third PMOS transistor MP3 becomes ON, and the input into the inverter G79 (namely, potential at the node N76) is HIGH. This level is inverted by the inverter G79, and as the output (namely, potential at the node N78) therefrom becomes LOW the NMOS transistor MN11 in the output circuit section 11g becomes OFF.
Accordingly, the output buffer circuit 12g enters in a high impedance state with respect to the input/output terminal 4. Therefore, a signal sent from an external device to the input/output terminal 4 can be delivered to the input buffer circuit 8 without loss.
When the second control signal IN3 is HIGH, the potential at the node N71 is always LOW regardless of the level of the first control signal IN2. This state is the same as that when the first control signal IN2 is LOW, and therefore both the PMOS transistor MP11 and the NMOS transistor MN11 in the output circuit section 11g are turned OFF regardless of the level of the output signal IN1. Accordingly, the output buffer circuit 12g enters in a high impedance state with respect to the input/output terminal 4, so that a signal sent from an external device to the input/output terminal 4 can be delivered to the input buffer circuit 8 without loss.
[Output Mode]
When the first control signal IN2 is at HIGH level, a LOW level signal obtained through inversion thereof by the inverter G71 is inputted into the NOR gate G72. When the second control signal IN3 as the other input signal into the NOR gate G72 is at LOW level, the output from the NOR gate G72 is HIGH, and is inputted into one of the input terminals of the NAND gate G74 as it is, and also inverted to LOW by the inverter G73 to be inputted into one of the input terminals of the NOR gate G75.
When the output signal IN1 is at LOW level, the output from the NAND gate G74, namely the node N73 is HIGH, and this state is the same as that in the case of input mode described above, and hence the PMOS transistor MP11 in the output circuit section 11g becomes OFF.
At that point of time, the output from the NOR gate G75, namely the node N74 enters HIGH, which is inverted to LOW by the inverter G77. Accordingly, the fourth NMOS transistor MN4 becomes ON and the third NMOS transistor MN3 becomes OFF, further the fourth PMOS transistor MP4 becomes OFF and the third PMOS transistor MP3 becomes ON, and the input into the inverter G79 is LOW. As this level is inverted by the inverter G79 to HIGH, the NMOS transistor MN11 in the output circuit section 11g becomes ON, and the LOW level signal is outputted to the input/output terminal 4.
When the first control signal IN2 is HIGH, the second control signal IN3 is LOW and the output signal IN1 is HIGH, two inputs into the NOR gate G75 are LOW and HIGH, so that output from the NOR gate G75, namely the node N74 is LOW, which is the same as that in the case of input mode described above, and hence the NMOS transistor MN11 in the output circuit section 11g becomes OFF.
At that point of time, the output from the NAND gate G74, namely the node N73 enters LOW, which is inverted to HIGH by the inverter G76. Accordingly, the first NMOS transistor MN1 becomes ON and the second NMOS transistor MN2 becomes OFF, further the first PMOS transistor MP1 becomes OFF and the second PMOS transistor MP2 becomes ON, and the input into the inverter G78 is HIGH. As this level is inverted by the inverter G78 to LOW, the PMOS transistor MP11 in the output circuit section 11g becomes ON, and the HIGH level signal is outputted to the input/output terminal 4.
FIG. 8 is a circuit diagram showing another configuration of the input/output circuit based on the conventional technology. This input/output circuit comprises an output buffer circuit 12h (a circuit section enclosed with a bold dashed line) having an input circuit section 10h (a circuit section enclosed with a dotted line) and an output circuit section 11h (a circuit section enclosed with a dot and dash line), and an input buffer circuit 8, and is connected to an input/output terminal (PAD) 4 and a static electricity protection circuit 7 similarly to the circuit of FIG. 7. The input/output terminal 4, static electricity protection circuit 7, and input buffer circuit 8 are the same as those having been described in the example based on the conventional technology shown in FIG. 7, and description thereof is omitted herein.
The input circuit section 10h comprises an input terminal 1 for receiving an output signal IN1; a first control terminal 2 for receiving a first control signal IN2; a second control terminal 3 for receiving a second control signal IN3; two inverters G81 and G83; two double-input NOR gates G82 and G85; a double-input NAND gate G84; six PMOS transistors MP1, MP2, MP3, MP4, MP5 and MP6; and six NMOS transistors MN1, MN2, MN3, MN4, MN5 and MN6. On the other hand, the output circuit section 11h comprises four inverters G86, G87, G88 and G89, a PMOS transistor MP11, and a NMOS transistor MN11.
In the example shown in FIG. 8, the VDD1 circuit driven by the first power supply potential VDD1 includes the input terminal 1; first control terminal 2; second control terminal 3; two inverters G81 and G83; two NOR gates G82 and G85; NAND gate G84; two PMOS transistors MP1 and MP4; and four NMOS transistors MN1, MN2, MN4 and MN5 each in the input circuit section 10h. On the other hand, the VDD2 circuit driven by the second power supply potential VDD2 (&gt;VDD1&gt;GND) includes the four PMOS transistors MP2, MP3, MP5 and MP6; two NMOS transistors MN3 and MN6 each in the input circuit section 10h; and the output circuit section 11h.
In FIG. 8, designated at 5a is a first power supply terminal for supplying the first power supply potential VDD1, at 5 a second power supply terminal for supplying the second power supply potential VDD2, at 6 a ground terminal for the ground potential GND; and at N81, N82, N83, N84, N85, N86, N87, N88, N89, N90, N91, N92, N93 and N94 are nodes.
The first control signal IN2 inputted from the internal circuit through the first control terminal 2 is inputted into a first input terminal of the NOR gate G82 through the inverter G81. While the second control signal IN3 inputted from the internal circuit through the second control terminal 3 is inputted into a second input terminal of the NOR gate G82. Output signal from this NOR gate G82 is inputted into a first input terminal of the NAND gate G84.
Inputted into a second input terminal of this NAND gate G84 is the output signal IN1 through the input terminal 1. Further, output signal from the NAND gate G84 is inputted into the gates of the first PMOS transistor MP1 and first NMOS transistor MN1.
The first PMOS transistor MP1 and the first NMOS transistor MN1 constitute a CMOS structure, and their drains are commonly connected to the source of the second NMOS transistor MN2. The sources of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected to the first power supply terminal 5a and the ground terminal 6 respectively. The gate of the second NMOS transistor MN2 is connected to the first power supply terminal 5a, and the drain thereof together with the drain of the second PMOS transistor MP2 is connected to the commonly connected gates of the third PMOS transistor MP3 and the third NMOS transistor MN3.
The source of the second PMOS transistor MP2 is connected to the second power supply terminal 5, and the gate thereof is connected to the commonly connected drains of the third PMOS transistor MP3 and the third NMOS transistor MN3, and also to the output circuit section 11h. The third PMOS transistor MP3 and the third NMOS transistor MN3 constitute a CMOS structure, and their sources thereof are connected to the second power supply terminal 5 and the ground terminal 6 respectively. A set of transistors with those MP1, MP2, MP3, MN1, MN2 and MN3 constitutes a signal level converting circuit.
On the other hand, an output signal from the NOR gate G82 is inputted into the first input terminal of the NOR gate G85 through the inverter G83, and the output signal IN1 is inputted into the second input terminal of the NOR gate G85. Output signal from this NOR gate G85 is inputted into gates of the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4.
The fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 constitute a CMOS structure, and their drains are commonly connected to the source of the fifth NMOS transistor MN5. The sources of the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 are connected to the first power supply terminal 5a and the ground terminal 6 respectively. The gate of the fifth NMOS transistor MN5 is connected to the first power supply terminal 5a, and the drain thereof together with the drain of the fifth PMOS transistor MP5 is connected to the commonly connected gates of the sixth PMOS transistor MP6 and the sixth NMOS transistor MN6.
The source of the fifth PMOS transistor MP5 is connected to the second power supply terminal 5, and the gate is connected to the commonly connected drains of the sixth PMOS transistor MP6 and the sixth NMOS transistor MN6, and also to the output circuit section 11h. The sixth PMOS transistor MP6 and the sixth NMOS transistor MN6 constitute a CMOS structure, and their sources are connected to the second power supply terminal 5 and the ground terminal 6 respectively. A set of transistors with those MP4, MP5, MP6, MN4, MN5 and MP6 constitutes a signal level converting circuit.
Output from the CMOS transistor comprising the third PMOS and NMOS transistors and output from the CMOS transistor comprising the sixth PMOS and NMOS transistors are inputted into each gate of the PMOS transistor MP11 and the NMOS transistor MN11 which constitute a CMOS structure through the inverters G86, G88 and the inverters G87, G89 respectively. Source terminals of the PMOS transistor MP11 and the NMOS transistor MN11 are connected to the second power supply terminal 5 and the ground terminal 6 respectively. The commonly connected drains of the PMOS transistor MP11 and the NMOS transistor MN11 are connected to the input/output terminal 4, static electricity protection circuit 7, and input buffer circuit 8.
Herein, each gate insulating film of MOS transistors constituting the five PMOS transistors MP2, MP3, MP5, MP6 and MP11, three NMOS transistors MN3, MN6 and MN11, and four inverters G86, G87, G88 and G89 in the output circuit section 11h respectively is formed so that each of the films is thicker than each gate insulating film of MOS transistors each constituting the two PMOS transistors MP1 and MP4, four NMOS transistors MN1, MN2, MN4 and MN5, two inverters G81 and G82, two NOR gates G82 and G85, and NAND gate G84 respectively, with which occurrence of dielectric breakdown is prevented.
Description is made for effects of the input/output circuit configured as shown in FIG. 8 separately in an input mode and an output mode thereof.
[Input Mode]
When the first control signal IN2 is at LOW level, the HIGH level signal obtained through inversion thereof by the inverter G81 is inputted into the NOR gate G82. The output from the NOR gate G82 (namely, potential at the node N81 and input into the NAND gate G84) is always LOW regardless of the level of the second control signal IN3. Then the output from the NAND gate G84 (namely, potential at the node N83) is always HIGH regardless of the level by the output signal IN1.
Accordingly, the first PMOS transistor MP1 becomes OFF and the first NMOS transistor MN1 becomes ON, and the third PMOS transistor MP3 becomes ON and the third NMOS transistor MN3 becomes OFF because input into the gates thereof is LOW. Thus, the output (namely, potential at the node N87) therefrom is HIGH and input into the gate of the PMOS transistor MP11 in the output circuit section 11h is HIGH, so that the PMOS transistor MP11 becomes OFF.
On the other hand, as the potential level at the node N81 is inverted by the inverter G83, the input into the NOR gate G85 (namely, potential at the node N82) is at HIGH level. The output from the NOR gate G85 (namely, potential at the node N84) is always LOW regardless of the level of the output signal IN1.
Accordingly, the fourth PMOS transistor MP4 becomes ON and the fourth NMOS transistor MN4 becomes OFF, and the sixth PMOS transistor MP6 becomes OFF and the sixth NMOS transistor MN6 becomes ON because input into the gates thereof is at HIGH level. Thus, the output (namely, potential at the node N92) therefrom is LOW and input into the gate of the NMOS transistor MN11 in the output circuit section 11h is LOW, so that the NMOS transistor MN11 also becomes OFF.
Accordingly, the output buffer circuit 12h enters in a high impedance state with respect to the input/output terminal 4. Therefore, a signal sent from an external device to the input/output terminal 4 can be delivered to the input buffer circuit 8 without loss.
When the second control signal IN3 is at HIGH level, the potential at the node N81 is always at a LOW level regardless of the level of the first control signal IN2. This state is the same as that when the first control signal IN2 is LOW, and hence both the PMOS transistor MP11 and the NMOS transistor MN11 in the output circuit section 11h becomes OFF regardless of the level of the output signal IN1. Accordingly, the output buffer circuit 12h enters in a high impedance state with respect to the input/output terminal 4, so that a signal sent from an external device to the input/output terminal 4 can be delivered to the input buffer circuit 8 without loss.
[Output Mode]
When the first control signal IN2 is at HIGH level, the LOW level signal obtained through inversion thereof by the inverter G81 is inputted into the NOR gate G82. When the second control signal IN3 as the other input signal into the NOR gate G82 is at LOW level, the output from the NOR gate G82 is at HIGH level, and is inputted into one of the input terminals of the NAND gate G84 as it is, and also inverted to a LOW level by the inverter G83 to be inputted into one of the input terminals of the NOR gate G85.
When the output signal IN1 is at LOW level, the output from the NAND gate G84, namely the node N83 is HIGH, and this state is the same as that in the case of input mode described above, and hence the PMOS transistor MP11 in the output circuit section 11h becomes OFF.
At that point of time, output from the NOR gate G85, namely the node N84 enters HIGH, and the fourth PMOS transistor MP4 becomes OFF and the fourth NMOS transistor MN4 becomes ON, and the sixth PMOS transistor MP6 becomes ON and the sixth NMOS transistor MN6 becomes OFF because input into the gates thereof is at LOW level. Thus, the output (namely, potential at the node N92) therefrom is at HIGH level and input into the gate of the NMOS transistor MN11 in the output circuit section 11h is HIGH, so that the NMOS transistor MN11 becomes ON, and the LOW level signal is outputted to the input/output terminal 4.
When the first control signal IN2 and second control signal IN3 are at HIGH and LOW level respectively and the output signal IN1 is at HIGH level, two inputs into the NOR gate G85 are at LOW and HIGH level, so that output from the NOR gate G85, namely the node N84 is LOW, which is the same as that in the case of input mode described above, and hence the NMOS transistor MN11 in the output circuit section 11h becomes OFF.
At that point of time, output from the NAND gate G84, namely the node N83 enters LOW, the first PMOS transistor MP1 becomes ON and the first NMOS transistor MN1 becomes OFF, and the third PMOS transistor MP3 becomes OFF and the third NMOS transistor MN3 becomes ON because input into the gates thereof is at HIGH level. Thus, the output (namely, potential at the node N87) therefrom is LOW and input into the gate of the PMOS transistor MP11 in the output circuit section 11h is at LOW level, so that the PMOS transistor MP11 becomes ON, and the HIGH level signal is outputted to the input/output terminal 4.
In the conventional type of input/output circuit as described above, when both the first power supply potential VDD1 and second power supply potential VDD2 are supplied thereto and an ordinary input/output operation is performed, potential levels of the node N75 and node N76 in the signal level converting circuit for the circuit shown in FIG. 7 are any of the combinations of HIGH and HIGH, LOW and LOW, and LOW and HIGH respectively. In the circuit shown in FIG. 8, potential levels of the node N87 and node N92 in the signal level converting circuit are any of the combinations of HIGH and HIGH, LOW and LOW, and HIGH and LOW respectively.
However, when the first power supply potential VDD1 is not ON in the initial state when the second power supply potential VDD2 is just turned ON, output from the circuit operating by the first power supply potential VDD1, namely from the VDD1 circuit is unstable and potential level in each section of the signal level converting circuit is not uniformly stabilized. For example, in the circuit shown in FIG. 7, potential levels of the node N75 and node 76 which are the two output terminals of the signal level converting circuit may become HIGH and LOW respectively.
Further, in the circuit shown in FIG. 8, potential levels of the node N87 and node 92 which are the two output terminals of the signal level converting circuit may become LOW and HIGH respectively. In such cases, there may arise a problem that the PMOS transistor MP11 and NMOS transistor MN11 provided at the final stage for output are concurrently turned ON, which causes an abnormal through current to flow between the second power supply 5 and ground 6 in the output buffer circuits 12g and 12h.